June 3Thur. → 5Sat. 2010
Tokyo Tech. Front (Kuramae kaikan), Tokyo Institute of Technology, Tokyo, JAPAN
Sponsored by Scientific Research on Priority Areas (No. 18063012, “Post-scaling”) from the Ministry of Education, Culture, Sports, Science and Technology in Japan
Silicon ultra-large scale integrated circuits (ULSIs) are now being faced to various physical limits on the scaling. Therefore, it is strongly required to establish the basic science and technology in realizing nano-scale complementary metal-oxide-semiconductor devices (Nano-CMOS) with high performance, new functionality and large-scale integration. For this purpose, Scientific Research on Priority Areas (No.18063012, "Post-scaling"), supported by the Ministry of Education, Culture, Sports, Science and Technology in Japan, have been conducted for 4 years starting in 2006. "ISTESNE" has been organized to offer an opportunity for discussions and exchange of recent progress through this research project and latest achievements of related regions. It is absolutely necessary to collaborate between the research communities for clearing the complex issues in the interdisciplinary research fields. ISTESNE is to be held in Tokyo Institute of Technology (Titech), Tokyo, Japan.
April 15, 2010 (Extended from March 31, 2010)
Shigeaki Zaima, Nagoya University
The Japan Society of Applied Physics, Division of Silicon Technology
The Japan Society of Applied Physics, Division of Plasma Electronics
The Japan Society of Applied Physics, Division of Thin Film and Surface Physics
The Institute of Electronics, Information and Communication Engineers, Electronics Society